Electronic timepiece alarms are known which include a driving circuit for providing signals of constantly reversing polarity to a piezoelectric crystal, thus causing the crystal to oscillate and produce an audible sound. It is also known that such piezoelectric alarms require a higher voltage for operation than is normally available from the timepiece energy cell itself. As a result, several circuit configurations have been devised to provide the higher voltage needed to drive the piezoelectric alarm.
One such configuration comprises the connection of the piezoelectric alarm to CMOS switches in an H-bridge circuit, a variation of which is disclosed in U.S. Pat. No. 4,068,461 "Digital Electronic Alarm Watch" (Fassett et al.) and shown in FIG. 1. A first inverter 93 includes a pair of MOS transistors 113 and 115, the gate electrodes 117 and 119 of these devices being connected to an input conductor 85 which carries a square wave signal varying from 0 to +V.sub.s, the supply voltage. The MOS transistor 113 is a P-channel device while the transistor 115 is an N-channel device, the source 121 of the transistor 113 and the drain 123 of the transistor 115 being connected to a front electrode 63 of a piezoelectric crystal 61. The drain 125 of the transistor 113 is connected to +V.sub.s. The source terminal 129 of the transistor 115 is connected to ground.
In a similar manner, a second inverter 91 includes a P-channel MOS transistor 131 and an N-channel MOS transistor 133, the gates 135 and 137 of these devices being connected in parallel to the input conductor 85. The source terminal 138 and drain terminal 139 of the transistors 131 and 133, respectively, are connected to an output line 95 of the second inverter 91. The source terminal 143 of the transistor 133 is connected to ground. The drain terminal 141 of the transistor 131 is attached to +V.sub.s.
The output line 95 from the second inverter 91 drives the gate terminals 145 and 147 of a P-channel MOS transistor 149 and an N-channel MOS transistor 151, respectively, of a third inverter 101. The source terminal 163 of the transistor 149 and the drain terminal 155 of the transistor 151 are connected to a second electrode 65 of the piezoelectric crystal 61. The drain terminal 157 of the transistor 149 is connected to +V.sub.s, while the source terminal 159 of the transistor 151 is connected to ground.
The prior art of FIG. 1 operates as follows. When the square wave varying between 0 and +V.sub.s volts on input line 85 is at +V.sub.s, the MOS transistors 113, 151 and 131 are nonconductive while the MOS transistors 115, 149 and 133 are conductive. The output line 95 from the second inverter 91 is thus clamped to ground. The output of the first inverter 93 on the front electrode 63 is likewise clamped to ground, while the output of the third inverter 101 on the second electrode 65 is maintained at +V.sub.s. In the remaining half cycle of the square wave input, when the input line 85 is clamped to ground, the MOS transistors 113, 151 and 131 are conductive while the transistors 115, 149 and 133 are nonconductive. The output line 95 from the second inverter 91 is clamped to +V.sub.s, as is the output of the first inverter 93 on the front electrode 63, while the output of the third inverter 101 on the second electrode 65 is at ground. Therefore, the polarity across the piezoelectric crystal 61 is reversed from the first half cycle of the square wave input, and the resulting peak-to-peak voltage across the crystal 61 is virtually doubled to +2 V.sub.s.
Another configuration is a voltage multiplying and inverting charge pump circuit shown in U.S. Pat. No. 4,807,104, issued on Feb. 21, 1989 and assigned to Motorola, Inc. This circuit 50 is illustrated in FIG. 2, and generally comprises a positive voltage portion 51 and a negative voltage portion 52. Positive voltage portion 51 comprises a switch 53 having a first terminal connected to a positive portion supply voltage terminal for receiving a positive power supply voltage, +V.sub.s. A second terminal of switch 53 is connected to a first electrode of a transfer capacitor 55 at a node 56. A second electrode of capacitor 55 is connected to a first terminal of a switch 57 at a node 58. A second terminal of switch 57 is connected to a ground reference terminal. A first terminal of a switch 60 is connected to the second terminal of switch 53 at a node 56. A second terminal of switch 60 provides a positive doubled output voltage, +2 V.sub.s, at a node 61. A switch 64 has a first terminal connected to node 58 and a second terminal connected to power supply voltage +V.sub.s. A first electrode of a reservoir capacitor 66 is connected to the second terminal of switch 60 at node 61, and a second electrode of capacitor 66 is connected to the power supply voltage for receiving +V.sub.s.
Negative voltage portion 52 comprises a switch 70 having a first terminal connected to node 56 and a second terminal connected to a node 71. A first terminal of a switch 72 is connected to the second terminal of switch 70. A second terminal of switch 72 is connected to the ground reference terminal. A first electrode of a reservoir capacitor 74 is connected to the second terminal of switch 72. A first electrode of a transfer capacitor 78 is connected to node 71, and a second electrode of transfer capacitor 78 is connected at a node 79 to a first terminal of a switch 80 and to a first terminal of a switch 82. A second terminal of switch 82 is connected to a ground reference terminal. A second terminal of switch 80 is connected to a second electrode of reservoir capacitor 74 at a node 86 which provides a negative doubled output voltage, (-2 V.sub.s). Each of switches 53, 57, 60, 64, 70, 72, 80 and 82 has a control electrode. The control electrode of switches 53, 57, 72 and 80 is coupled to a control signal .PHI..sub.1, and the control electrode of switches 60, 64, 70 and 82 is coupled to a control signal .PHI..sub.2. Control signals .PHI..sub.1 and .PHI..sub.2 are nonoverlapping clock signals.
In operation, charge pump 50 has first and second periods of operation as defined by the logic states of control signals .PHI..sub.1 and .PHI..sub.2. During a first period of circuit operation, control signal .PHI..sub.1 has a high logic state and control signal .PHI..sub.2 has a low logic state. During the first period of circuit operation, switches 53, 57, 72 and 80 are conductive and switches 60, 64, 70 and 82 are nonconductive. During a second period of circuit operation, control signal .PHI..sub.1 has a low logic state and control signal .PHI..sub.2 has a high logic state. During the second period of circuit operation, switches 53, 57, 72 and 80 are nonconductive, and switches 60, 64, 70 and 82 are conductive.
In the positive voltage portion 51 during the first period of circuit operation, capacitor 55 charges to a voltage equal to the supply voltage V.sub.s via switches 53 and 57. During the second period of circuit operation, transfer capacitor 55 is disconnected from between ground and V.sub.s. The second electrode of transfer capacitor 55 is negatively charged and is connected to supply voltage V.sub.s by switch 64. As a result, the first electrode of transfer capacitor 55 which is positively charged is translated to a doubled transfer voltage of (+2 V.sub.s). The doubled transfer voltage across transfer capacitor 55 is charge shared onto reservoir capacitor 66 via switches 60 and 64. Reservoir capacitor 66 is permanently connected between power supply voltage V.sub.s and the positive doubled output voltage, (+2 V.sub.s) at node 61. The charge on reservoir capacitor 66 is added with the power supply voltage V.sub.s to provide a continuous positive output voltage equal to (+2 V.sub.s) at node 61.
In the negative voltage portion 52, during the second period of circuit operation the transfer voltage, (+2 V.sub.s) at node 56 is charge shared onto transfer capacitor 78 via switches 64, 70 and 82. Subsequent to the second period of circuit operation, transfer capacitor 78 is disconnected from the (+2 V.sub.s) transfer voltage. The first electrode of transfer capacitor 78 at node 71 is positively charged with respect to ground and is connected to ground during a successive first period of circuit operation. The voltage across transfer capacitor 78 is translated and the negatively charged second electrode of transfer capacitor 78 is at a voltage potential of (-2 V.sub.s). The (-2 V.sub.s) voltage of transfer capacitor 78 is charge shared onto reservoir capacitor 74 via switches 72 and 80. Reservoir capacitor 74 is always connected between the ground reference and node 86 to provide a continuous negative output voltage of (-2 V.sub.s).
Charge pump 50, as disclosed in the '104 patent, may be expanded to include other voltage doubling circuit portions for further doubling the power supply voltage from 2 V.sub.s to additional integer multiples of V.sub.s. This requires utilization of additional components. If such a circuit extension is desired, duplicates of charge pump circuit 50 may be provided with the 2 V.sub.s transfer voltage of charge pump 50 used as the power supply voltage for the additional circuitry.
Although the operation of the aforementioned circuits have proven acceptable in certain timepiece applications, it is found that because of design limitations, aesthetic considerations, and overall timepiece economics, these circuit designs have several drawbacks. Specifically, as it is known that advances in increased integrated circuit density have been made in recent years, and that thinner wristwatches are perceived by the consumer to be more aesthetic, much effort has been made to decrease the size of a timepiece by reducing the number of electronic components within the timepiece and including as many components on the timepiece integrated circuit chip as possible.
The H-bridge configuration of FIG. 1 is disadvantageous because it requires that both terminals of the piezoelectric alarm be isolated from the timepiece energy cell, and also that the alarm be insulated from the timepiece caseback. As it is found that a more inexpensive and less complex construction of a piezoelectric alarm transducer circuit involves the connection of the piezoelectric alarm directly to the caseback and energy cell via conducting ink or epoxy, (thereby using the timepiece caseback or bezel to produce the audible sound), use of the H-bridge configuration would require that additional contacts be made from the piezoelectric alarm to the battery. This would unnecessarily add to both the expense and the complexity of the timepiece alarm during manufacture of the timepiece. Furthermore, utilizing an H-bridge circuit limits the output voltage to approximately twice the supply voltage. Consequently, the loudness of the alarm may be unsatisfactory.
The charge pump circuit of FIG. 2, while permitting higher output voltages than the H-bridge circuit, requires the use of many components, including the need for multiple capacitors. Thus, given the paramount importance of reducing the size of a timepiece, this circuit design is not optimal for driving a piezoelectric alarm.
Therefore, it is an object of the present invention to provide a high voltage output circuit and method for driving a piezoelectric alarm within a timepiece which minimizes the number of components and thus, the size of the timepiece itself.
It is another object of the present invention to minimize the number of components extraneous to the timepiece integrated circuit.
A further object of the present invention is to provide a simple and efficient means to boost voltage for driving a piezoelectric alarm without isolating the piezoelectric crystal from the battery or timepiece caseback.